1. Field of the Invention
The present invention relates to a variable delay circuit such as a digital DLL (Delayed Locked Loop) circuit, and a semiconductor integrated circuit device equipped with such as a DLL circuit.
Recently, there has been considerable advance of the operation speed and integration density of semiconductor integrated circuit devices. Under the above situation, it is required to provide a clock signal synchronized with an external clock signal to a given circuit. More particularly, a synchronous DRAM device (hereinafter simply referred to as an SDRAM device) is required to supply a clock signal synchronized with an external clock signal to output buffer circuits. Such a clock signal can be obtained through a DLL circuit, which receives the external clock signal. As the frequency of the DLL circuit is increased, the DLL circuit is required to be configured with higher precision. In order to meet the above requirement, the DLL circuit should be equipped with a variable delay circuit having high precision.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional variable delay circuit. The circuit shown in FIG. 1 includes a plurality of delay elements, for example, 10 delay elements G1 through G10, which are connected in series. Hereinafter, the delay elements G1 through G10 are referred to as gates. Each of the gates G1 through G10 has a unit delay time td. The inputs of the gates G1 through G10 are operably connected to an input node IN through switches SW1 through SW10, respectively. The output of the gate G10 is connected to an output node OUT.
The ON/OFF of the switches SW1 through SW10 are controlled by a control circuit, which is not shown in FIG. 1. The control circuit closes one of the switches SW1 through SW10 in accordance to a necessary delay time. In FIG. 1, only the switch SW7 is closed. A signal applied to the input node IN passes through four gates G7 through G10 and is thus delayed by 4td. That is, the output signal obtained at the output node OUT lags behind the input signal applied to the input node IN by 4td. The variable delay circuit is capable of defining the delay time between td and 10td by selecting one of the switches SW1 through SW10.
It should be noted that the variable delay circuit shown in FIG. 1 can provide the delay times equal to an integer multiple of the unit delay time td. In other words, the variable delay circuit shown in FIG. 1 cannot define the delay time at a precision (step) less than the unit delay time td. For example, the circuit cannot define a delay time of 2.5td.
If a semiconductor integrated circuit device such as an SDRAM device operates at a relatively low operation frequency, the conventional delay circuit shown in FIG. 1 can be equipped with the device. The digital DLL circuit built in the SDRAM device produces an internal clock signal synchronized the external clock signal. Hence, an influence of a clock signal line formed on the SDRAM device can be eliminated from the internal clock signal, and data can be output to the outside of the device in synchronism with the external clock signal. However, if the SDRAM device is required to operate at a frequency as high as 100 MHz, the DLL circuit which should be mounted on the SDRAM device is required to have a capability of finer delay control.
As has been described previously, the digital DLL circuit has a delay circuit made up of a plurality of gates (unit delay circuits) connected in series, the gates being formed of logic gates. Usually, the unit delay circuit has a minimum delay time approximately equal to 200 ps. In order to realize the SDRAM device which operates at an operation frequency equal to or higher than 100 MHz, the digital DLL circuit is required to realize a fine delay control in which a delay time less than 200 ps can be controlled. In principle, the precision of the delay control can be improved by using a unit delay circuit having a delay time less than 200 ps.
However, the DLL circuit employing such a fine unit delay circuit requires a large number of unit delay elements in order to ensure a certain delay time. In this case, an increased circuit scale should be realized on the chip.